Thin gate dielectric reliability and integrity constitute one of the major challenges and concerns for the development and manufacturing of VLSI (very large scale integration) and ULSI (ultra large scale integration) semiconductor products. The development of reliable and high quality thin gate dielectrics requires a research- and time-intensive effort to meet continuously evolving competitive demands for smaller device geometries and better performance and reliability. As the thickness of the gate dielectric continues to be reduced to meet industry demands, continuous process improvements are necessary to meet yield and reliability criteria. The selection of optimum gate dielectric processes demands an intensive effort to collect life stress data on the wafers produced by the various processes.
It is currently known to collect life stress data using a chip-by-chip stress procedure in which each chip is contacted with a probe, one at a time, to measure the effects of lifetime-accelerated voltage and temperature conditions. A wafer typically contains a plurality of chips repeatedly patterned across its surface, a chip being a basic integrated circuit device unit. All chips on a wafer are initially tested at actual-use voltage conditions to establish the initial quality of gate dielectric. Then, voltage and temperature stresses are applied to each chip for a certain amount of time ranging from a few minutes to several hours or more. After the application of accelerated life stress conditions, the chips are tested again, and a significant increase in gate leakage from its initial value signifies dielectric breakdown.
Using advanced modeling, the stress data is then extrapolated to a projection of reliability under actual-use conditions. This projection is used to make comparisons between various process options. Because the manufacturing process does not permit time-consuming testing of each chip of every wafer produced, random sampling with relatively short testing periods is required. Still, the chip-by-chip contacting system is a labor- and time-intensive process and contributes significantly to the overall development cost. An evaluation procedure is needed whereby the quality of the dielectric on the whole wafer may be evaluated, especially an evaluation procedure that may be conducted before the fabrication of the electronic devices.